How to write a Verilog code for 2:1 Mux?

by Praful Kharade Posted on

In the realm of digital circuit design, multiplexers play a pivotal role in data routing and selection. Among the various types of multiplexers, the 2:1 multiplexer is a fundamental building block that selects one of two input signals based on a control signal. In this detailed walkthrough, we’ll dissect the Verilog implementation of a 2:1 multiplexer, exploring each aspect of the code and providing a comprehensive explanation of its functionality.

Run on EDA Playground

The Verilog Code:

Setting Up the Module:

Verilog
module mux21(clk, reset, in, out, sel);
  
  input clk, reset, sel;
  output reg out;
  input [1:0] in;
  • Let’s imagine this module as the heart of our multiplexer. It’s like the control center that manages all the inputs and outputs.
  • We have inputs for the clock signal (clk), reset signal (reset), and selection signal (sel), along with a 2-bit input vector (in) and an output register (out).

Managing the Logic:

Verilog
always @(posedge clk) begin
    
    if(reset) begin
      out <= 1'b0;
    end
    
    else if(sel == 0) begin
      out <= in[0];
    end
    
    else begin
      out <= in[1];
  	end    

  end
  • Now, let’s think of this part as the brain of our multiplexer. It’s where all the decision-making happens!
  • When the reset signal is active, it’s like hitting the reset button. Our output (out) goes back to zero.
  • If the selection signal (sel) is low (0), we choose the first input (in[0]).
  • Otherwise, we go with the second input (in[1]).

Here is the complete Verilog code Design code

Verilog
// Code by Praful Kharade
// Logicflick.com
module mux21(clk, reset, in, out, sel);
  
  input clk, reset, sel;
  output reg out;
  input [1:0] in;
  
  always @(posedge clk) begin
    
    if(reset) begin
      out <= 1'b0;
    end
    
    else if(sel == 0) begin
      out <= in[0];
    end
    
    else begin
      out <= in[1];
  	end    

  end
endmodule

It’s Time to write a Test bench to verify the Design

The Testbench Code

Setting up the Testbench

Verilog
module tb;
  
  reg clk, reset, sel;
  reg [1:0] in;
  wire out;
  
  mux21 instance1 (clk, reset, in, out, sel);
  • Think of this as our playground where we test our multiplexer in different scenarios.
  • We’ve got registers (reg) for our control signals and input, and a wire (wire) for our output.
  • Our multiplexer module (mux21) is like the toy we’re testing in our playground.

Playing with Scenarios:

Verilog
  initial begin
    clk = 0;
    reset = 1;
    in = 2'b00;
    sel = 1;
    #10;
    // Additional test scenarios
  end
  • Here’s where the fun begins! We set up different situations to see how our multiplexer behaves.
  • We start with a reset and give it some time (#10) before changing the inputs and selection signal for the next scenario.

Here is the Complete Test Bench code

Verilog
//Code by Praful Kharade
// Logicflick.com
module tb;
  
  reg clk, reset, sel;
  reg [1:0] in;
  wire out;
  
  mux21 instance1 (clk, reset, in, out, sel);
  
  always #5 clk = ~clk;
  
  initial begin
    clk = 0;
    reset = 1;
    in = 2'b00;
    sel = 1;
    
    #10;
    reset = 0;
    in = 2'b10;
    sel = 0;
    #10;
    
    reset = 0;
    in = 2'b01;
    sel = 1;
    #10;
    
    reset = 0;
    in = 2'b11;
    sel = 1;
    #10;
    
    
    reset = 0;
    in = 2'b00;
    sel = 1;
    #10;
    
    
  end
  
  initial begin
    $dumpfile("dump.vcd");
    $dumpvars(1);
    
  end
  
  initial begin
    
    #100;
    $finish;
    
  end
  
endmodule

To wrap up

In this friendly journey, we’ve uncovered the inner workings of a 2:1 multiplexer using Verilog. By understanding each part of the code and testing it in various scenarios, we’ve gained valuable insight into how digital systems make decisions and process data. So next time you use your computer, remember the humble multiplexer quietly doing its job behind the scenes.