Fixed-Size Arrays in SystemVerilog

by Praful Kharade Posted on

Arrays are essential in digital design languages like SystemVerilog, allowing you to organize data into sequences of values. Arrays enable efficient management of groups of variables under a single name, making the code more readable and easier to manage. Among the various types of arrays in SystemVerilog, fixed-size arrays are straightforward and frequently used.

In this blog, we’ll delve deep into fixed-size arrays, understanding their characteristics, syntax, and practical usage through a simple code example.

What is a Fixed-Size Array?

A fixed-size array in SystemVerilog is an array where the number of elements is predefined and does not change during runtime. The size of the array is fixed at the time of declaration and remains constant throughout the simulation.

Each element in the array can be accessed using an index, starting from 0 up to N-1, where N is the size of the array.

Syntax for Fixed-Size Arrays

Verilog
data_type array_name [size];
  • data_type: The data type of the array elements (e.g., bit, logic, int, etc.)
  • array_name: The name of the array
  • size: The fixed number of elements the array can hold.
Verilog
bit [7:0] myArray [10];

This declares an array called myArray with 10 elements, each element being 8 bits wide.

Key Characteristics of Fixed-Size Arrays

  • Predefined Size: The number of elements is known at compile-time, which simplifies memory management and guarantees a bounded memory requirement.
  • Indexing: The elements are accessed using zero-based indexing. For an array of size N, valid index values range from 0 to N-1.
  • Homogeneous Elements: All elements in a fixed-size array have the same data type, ensuring uniformity of data.

Example: Fixed-Size Array in SystemVerilog

Let’s go through a simple example of a fixed-size array in SystemVerilog and understand its functionality.

Code Example

Verilog
module fixed_size_array_example;
  bit [7:0] myArray[10]; // Array of 10 elements, each 8 bits wide

  initial begin
    // Assign values to the fixed-size array
    for (int i = 0; i < 10; i++) begin
      myArray[i] = i * 2; // Assign even numbers to the array
    end

    // Display values
    $display("Fixed-size Array Values:");
    for (int i = 0; i < 10; i++) begin
      $display("myArray[%0d] = %0d", i, myArray[i]);
    end
  end
endmodule

Explanation:

  1. Array Declaration:
Verilog
bit [7:0] myArray[10];

Here, myArray is a fixed-size array with 10 elements. Each element is 8 bits wide, which can hold values ranging from 0 to 255.

Assigning Values to the Array:

Verilog
for (int i = 0; i < 10; i++) begin
  myArray[i] = i * 2; // Assign even numbers to the array
end

A for loop is used to assign values to the array. Each element is assigned an even number, starting from 0. For instance:

  • myArray[0] = 0
  • myArray[1] = 2
  • myArray[2] = 4
  • and so on, up to myArray[9] = 18.

Displaying Array Values:

Verilog
$display("Fixed-size Array Values:");
for (int i = 0; i < 10; i++) begin
  $display("myArray[%0d] = %0d", i, myArray[i]);
end

Another for loop is used to print each element of the array using the $display system task. The %0d format specifier displays the index (i) and the corresponding value (myArray[i]).

You can also try the code on EDA Playground by clicking the link below

EDA Playground

Output

When you run the above code, you will see the following output:

Verilog
Fixed-size Array Values:<br>myArray[0] = 0<br>myArray[1] = 2<br>myArray[2] = 4<br>myArray[3] = 6<br>myArray[4] = 8<br>myArray[5] = 10<br>myArray[6] = 12<br>myArray[7] = 14<br>myArray[8] = 16<br>myArray[9] = 18<br>

This output shows that each element of the array was successfully initialized with the expected value (even numbers).

Advantages of Using Fixed-Size Arrays

  1. Simplicity: Since the size is predefined, fixed-size arrays are easier to implement and manage in hardware description languages.
  2. Deterministic Memory Usage: The size of the array and the data type are known at compile-time, allowing deterministic memory allocation.
  3. Predictable Indexing: Since the array size is fixed, accessing elements using an index is predictable and ensures no runtime surprises.

Common Use Cases for Fixed-Size Arrays

  • Register Files: In digital designs, register files are often implemented using fixed-size arrays. Each register can be treated as an element of the array.
  • Look-Up Tables (LUTs): Arrays are used to store precomputed values in LUTs, where each entry is accessed using an index.
  • Data Buffers: Fixed-size arrays can serve as data buffers, storing data temporarily during communication between different hardware blocks.

Conclusion

Fixed-size arrays in SystemVerilog provide a straightforward way to handle groups of variables under a single name. They are easy to declare and use, and they provide the benefit of fixed memory allocation, which is crucial in hardware design. Understanding how to manipulate arrays efficiently is an essential skill for any hardware or digital design engineer.

In this blog, we explored the basic structure of fixed-size arrays with a practical example. Fixed-size arrays are versatile and widely used in digital designs, so mastering them will serve you well in any hardware development project.

Feel free to experiment further by changing array sizes, data types, or initialization patterns to see how fixed-size arrays behave in different scenarios!