Portfolio

by Praful Kharade Posted on

My Resume

Working Experience

August 2023 – Present

16-Bit UART Serial Communication Protocol Implementation

VLSI Design Project

• Developed a robust 16-bit UART serial communication protocol using Verilog at the RTL level to facilitate dependable data exchange between devices, following the ASIC design flow.

August 2023 – Present

Custom Standard Cell Library Design

Using Cadence Virtuoso

• Created a custom standard cell library using Cadence Virtuoso, incorporating a diverse array of logic gates to enhance functionality and performance as part of the ASIC design flow.

August 2023 – Present

Sequential LSB to MSB Data Bit Transmission

Data Transmission System

• Implemented a data transmission system ensuring sequential transmission of data bits from the Least Significant Bit (LSB) to the Most Significant Bit (MSB), complete with start and stop bits for synchronization.

August 2023 – Present

Precise Timing and Synchronization

Using Verilog

• Utilized Verilog to manage timing and synchronization, guaranteeing efficient and error-free 16-bit data exchange within the hardware design project, adhering to ASIC design protocols.

My Resume

Working Experience

Date Range

Design and Verification of FIFO, I2C Protocols

SystemVerilog

• Developed SystemVerilog test bench: Created a test bench to verify FIFO-based and I2C digital systems using drivers, monitors, and scoreboards. Implemented reset, write, and read operations with mailbox communication.
• Designed comprehensive verification environment: Built a UVM-based environment to ensure accurate DUT verification, incorporating randomized stimulus and protocol adherence checks for both FIFO and I2C interfaces.

Date Range

Design and Verification of UART Protocol

SystemVerilog

• Developed SystemVerilog test bench: Created a test bench for UART using drivers, monitors, and scoreboards. Implemented UART operations including initialization, transmission, and reception with mailbox communication.